1. Field of the Invention
The present invention relates to a semiconductor device that includes a semiconductor chip having an outside surface on which an encapsulating resin layer is formed.
2. Description of the Related Art
The downsizing of portable electronic equipment in recent years has made it imperative to miniaturize the semiconductor devices used in such equipment. In response to this need, there have emerged semiconductor devices called “chip size packages” which have nearly the same external dimensions as a semiconductor chip. Chip size packages exist in a number of forms, one of which is known as a “wafer-level chip size package” or “wafer-level chip scale package.” Such packages are referred to below by the acronym ‘W-CSP.’
Current trends in semiconductor device design include not only increasing of the number of gates but also reducing of simultaneous switching noise during the high-speed operation of LSI chips. To these ends, the power supply and the number of ground pins are tried to increase, and the inductance is tried to decrease. In state-of-the-art devices, sometimes 50% or more of the pins are in fact used as power supply grounds.
Japanese Patent Kokai (Laid-open Application) No. 2000-243785 and No. 2003-17530 teach use of dummy bumps which are not electrically connected to the integrated circuit, in order to prevent semiconductor chip deformation due to pressure exerted by the encapsulating resin.